The present invention relates generally to semiconductor processing and, more particularly, to methods of processing array and support areas of a vertical transistor pass gate dynamic random access memory (DRAM).
A dynamic random access memory (DRAM) circuit usually includes an array of memory cells interconnected by a number of rows and columns. These rows are commonly referred to as wordlines (WLs) while the columns are referred to as bitlines (BLs). Activating selected ones of these wordlines and bitlines allows the reading of data from or the writing of data to memory cells.
Typically, a DRAM memory cell comprises a metal oxide semiconductor field effect transistor (MOSFET) connected to a capacitor, such as a vertical MOSFET having a trench capacitor. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate. This perpendicular feature enables an effective cell size reduction with an increase in bit densities. As such, the use of vertical MOSFETs have been proposed to overcome the scalability limitations of planar MOSFET DRAM access transistors.
In vertical transistor DRAM chips, the process steps of the array and support areas of the chip are performed separately during manufacture. For example, in the formation of a memory cell in vertical MOSFET DRAM arrays, an array top oxide (ATO) is needed to isolate the passing word-lines from active areas on the substrate. An ATO layer is generally formed by two different methods as known in the art.
One such method for forming the ATO is referred to as a top oxide early (TOE) process. In TOE processing, an array top oxide area is formed with pad nitride being present in the support regions. Subsequently, this pad nitride is stripped in the support areas, a gate oxide is grown and then a gate poly is deposited. While this scheme has the advantage of completely decoupling the array and support processing, it is complex and requires many processing steps in the careful optimization of the location of the block masks required for formation of the ATO.
Another method for forming the ATO is referred to as a Top Oxide Late (TOL) process. In TOL processing, the ATO is deposited after the support gate oxidation and polysilicon deposition. While TOL processing reduces the number of processing steps and manufacturing costs, it undesirably changes the gate oxide during ATO deposition. In addition, the planarizing the ATO down to the gate polysilicon within the support regions can lead to undesirable residual patterns in the support region.
Another disadvantage with the above prior art techniques of forming ATO layers is that, in each method, the ATO is in direct contact with the isolation trench (IT) fill in the array area. During the subsequent steps of processing the array area, voids or divots may undesirably form in dense array areas which adversely affect production yields.
Consequently, a need continues to exist in the art for improved methods of forming ATO layers.
The present invention overcomes the above problems and deficiencies in the prior art by disclosing a simplified method of providing an ATO in a vertical MOSFET DRAM in a manner that reduces the number of processing steps, complexity and costs, while simultaneously improving production yield.